Implemented a fully functional 32-bit RISC-V CPU in Logisim Evolution, including core modules such as the ALU (arithmetic, logic, shift, multiply), Register File with 32 registers (x0 hardwired to zero), Immediate Generator, Control Logic, and aligned Data Memory with write masks. The design was extended into a two-stage pipelined processor (IF, ID/EX/MEM/WB) with branch flush handling, supporting arithmetic, load/store, branch, and jump instructions.
During the process, I learned to carefully examine Logisim components and design datapath hierarchies. For example, splitters and sign-extenders were essential in implementing shifters and multiplication, while DeMux and tunnels simplified the Register File wiring. Building the single-cycle datapath helped me understand instruction fields and immediate generation, and later extending it to a pipeline taught me how to manage flushes and control hazards.
The most challenging part was memory alignment and write masks: handling unaligned addresses required bit manipulation and edge-case debugging. Finally, extensive testing with provided harnesses, custom testbenches, and community feedback helped uncover subtle bugs that normal cases did not reveal. Overall, this project gave me hands-on experience in computer architecture, datapath construction, and debugging a working CPU from the ground up.

CPU (Top-Level) – Connects all modules into the full datapath and pipeline.

ALU – Performs arithmetic, logic, shift, and multiply operations.

Branch Comparator – Evaluates branch conditions (e.g., beq, blt, bge).

Control Logic – Decodes opcode and funct3/funct7 to generate control signals.

CSR – Control and Status Registers, including tohost for test output.

Immediate Generator – Reconstructs immediates for I/S/B/U/J type instructions with sign-extension.

Memory Unit – Handles loads/stores with byte/halfword/word alignment and write masks.

Register File – Implements 32 registers (x0 hardwired to zero) with read/write ports.

RISC-V CPU Design

Overview

Details